Lip-Bu Tan
Analyst · Griffin Securities
Good afternoon, everyone, and thank you for joining us. Cadence delivered solid results in Q2. Total revenue was $362 million. Non-GAAP operating margin was 24%, and operating cash flow was $75 million. This result reflects our ability to support our customers' needs to innovate and invest in new design activities. They also reflect the strength of our organization, our products and our customer relationships. As had been the case for the past 3 years, the environment continues to be challenging, with macro uncertainty and softness in semiconductors. Despite that, most of our customers continue to innovate and invest in new design activities. Now let us review some of the Q2 highlights. Our customers expect Cadence to collaborate with them and their ecosystems as they develop, design and build their great products. They look to us for innovative design solutions. Today, I will highlight 2 of our recent internally developed innovations, one in timing signoff and the other in custom/analog design. I will also highlight our progress in IP as we closed additional acquisitions in Q2 and sign our largest design IP contract to date. Timing signoff is a critical step in the design flow. We introduced Tempus, a breakthrough static timing analysis and closure tool. It will enable system-on-a-chip developers to accelerate timing closure and to move their chip design to fabrication more quickly. Tempus used a massive distributed parallel engine that can scale across hundreds of CPUs to deliver up to 10x faster performance than traditional timing analysis solutions. It can handle designs with hundreds of millions of objects without compromising accuracy and deliver faster and more accurate design closure and signoff. TSMC certified Tempus for signoff on their 20-nanometer processes. Having a powerful timing signoff solution will complement Encounter, our digital design platform. In custom/analog, we are extending our leadership by continuing to invest in more automated solutions and addressing advanced nodes into FinFET. We recently introduced an electrically-aware design capability in the Virtuoso custom design platform. This is a ground-breaking approach to custom/analog design. It provides electrically-aware feedback during layout design. This enables engineers to reduce their design cycle up to 30%, in addition to optimizing chip size and performance. Earlier this month, we announced that TSMC expanded their collaboration with Cadence for custom/analog design. TSMC deployed Virtuoso for advanced nodes into 16-nanometer FinFET designs. TSMC will create and deliver native SKU-based process design kits, also known as PDK. PDKs will provide -- these PDKs will provide the best user experience and the highest level of accuracy for Virtuoso customers. As you know, growing our IP business is a key focus for Cadence. In Q2, we expanded our IP portfolio. In addition to the Tensilica acquisition, we closed the acquisitions of Cosmic Circuits and the Evatronix IP business. These acquisitions add complementary USB and MIPI IP that is silicon proven at advanced nodes. They also bring us talented development teams in India and Poland. We'll begin integrating Tensilica, Cosmic Circuits and Evatronix IP business with earlier acquisitions and our internal development teams. As a result, Cadence now offers a broad IP portfolio that addresses the IP requirements of our customers. We've demonstrated this by signing our largest design IP contract so far, a multimillion dollar deal with an Asian customer. This contract includes a combination of products such as TDR, MIPI, USB IP. The MIPI and USB IP are from Cosmic Circuits. Our Tensilica business is off to a good start with a strong quarter. The transition had been smooth, and the customer interest, engagement and orders are strong. Our verification IP, or VIP, business continues to be strong. We work closely with the standards bodies so that we can introduce new VIP and memory models at or even before the ratification of the newest protocols. New VIP introduced this quarter includes HDMI 2.0, mobile PCI Express and WIO 2.0. Finally, I wanted to provide an update on the acquisition of Sigrity, which we completed a year ago. Sigrity is contributing to the renewed growth of our printed circuit board, or PCB, business. Our PCB business is reaching an inflection point as customers move to high-speed design for mobile, consumer and cloud infrastructure segments. The combination of our Allegro product line plus Sigrity power, signal and thermal analysis gives us a complete solution to address the requirements for development of high-speed products. For the first half of 2013, our PCB and IC packaging revenue was up more than 30% over the first half of 2012. In summary, this quarter, we introduced 2 innovative products in the digital and custom/analog domains. We closed 3 previously announced IP acquisitions and now have the critical mass needed to address more of our customers' IP requirements. We are continuing to attract top talent to Cadence, both through hiring and acquisitions, which keeps strengthening our innovation engine. We continue to drive excellent operational and financial performance, as today's results demonstrate. Now I will turn the call over to Geoff to review the financial results and provide our outlook.