Lip-Bu Tan
Analyst · BoA ML
Good afternoon, everyone, and thank you for joining us. Cadence delivered strong results in Q1. Total revenue was $354 million. Non-GAAP operating margin was 24%, and operating cash flow was $75 million. The environment is challenging, with macro uncertainty and softness in semiconductors. Despite that, many of our customers continue to innovate and invest in new design activities. They are looking to Cadence to collaborate more closely with them and their ecosystems to help build great products that drive their success. Today, I will highlight our progress in IP, advanced node design and verification. Expanding our IP business is strategic focus for Cadence. Recently, we took several important steps. The acquisition of Tensilica significantly expand the scope of our IP business by adding configurable dataplane processing units. Tensilica has an attractive loyalty model and serves fast-growing end markets via by mobile wireless, network infrastructure, audio infotainment and home applications. In February, we announced our intent to acquire Cosmic Circuits, which will add significant silicon-proven analog and mixed signal IP to our portfolio. This includes IP for USB, MIPI, audio and Wi-Fi standards. We expect that transaction to close soon. Last month, we acquired a talented team of approximately 25 analog IP designers that are specialized in development of SerDes blocks for high-speed interfaces. Last year, we shifted significant numbers of highly skilled analog designers from our service business into R&D to develop commercial IP and accelerate delivery on our IP roadmap. Many of these designers have more than a decade of experience developing high-speed interfaces such as SerDes. Along with high-quality IP and impressive customer list, each of these acquisitions adds very talented and experienced developers to the growing IP R&D team at Cadence. When all these acquisitions close, we will have over 600 engineers in our SoC Realization group. We see a natural synergy between our IP and core EDA business. We intend to optimize our EDA tools to our IP and our IP to our tools. In addition, we will use our worldwide channel to sell IP to the same customers who buy EDA tools. Our investment in IP will enable customers to focus on developing differentiable technology while leveraging proven Cadence IP to complete the advanced SoCs. Given the industry trend towards more outsourcing of standards-based IP, we expect strong growth in our IP business. Next, I want to highlight our capabilities and progress in products for advanced node design. Cadence is collaborating with ARM and leading foundry partners to help extend Moore's Law by enabling both FinFET base and 3D-IC base design to our industry-leading design flows and IP. FinFET technology now being used at 16- and 14-nanometer process nodes will help deliver the power, performance and area advantages and the economics needed to extend Moore's Law. Cadence has developed unique expertise in FinFET technology through a deep collaboration with industry-leading IT providers and foundries. Recently, we announced a successful collaboration with ARM to implement the industry's first Cortex-A57 64-bit processor on TSMC's 16-nanometer FinFET process and a multiyear agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology targeting advanced node designs for mobile, networking, servers and FPGA applications. Beginning earlier in the design process and future, we will collaborate with TSMC to address the design challenges, specifically to FinFET, to enable ultra low-power high-performance chips. Our Encounter digital platform Virtuoso custom analog platform and signoff solutions are all FinFET-enabled and foundry-qualified. Our investment in preparing for FinFET technology is providing new opportunities for Cadence to engage with the leading semiconductor companies. Now let us review our progress in verification. Higher complexity, increased integrations of IP blocks into an SoC and strengthening time-to-market windows are driving rapid growth in the demand for verification solutions, analog, digital, mixed signal or hardware-assisted. Palladium XP has been one of our most successful products ever, thanks to its rapid adoption. Since it was introduced in 2010, Palladium XP today has more than 4x the installed capacity worldwide than the last 2 generations of Palladium combined. This shows the rapid growing needs for emulation to develop, verify and validate complex SoCs and systems. In addition to new users, a substantial portion of Palladium XP sales have been repeat orders from top-tier customers as they continue to deploy more systems to accelerate hardware, software co-design, co-development to meet aggressive time-to-market goals for their products. In Q1, our Palladium XP business was categorized by a number of significant repeat orders with leading semiconductor companies, including Qualcomm. Another customer has expanded its footprint, by 35 systems over the past 18 months through multiple orders. In summary, Cadence is innovating in multiple areas in collaboration with ecosystem partners and customers to help meet the needs of our customers to build great products. We are continuing to attract the best talent to our engineering community, both through hiring and acquisitions. We continue to drive excellent financial and operational performance. Now I will turn the call to Geoff to review financial results and provide our outlook.