Aart J. de Geus
Analyst · Needham & Company
Good afternoon, and thank you for taking the time to join us. Synopsys continues to perform very well and in Q3, we again delivered solid results in terms of business, technology and customers, meeting or beating every target we communicated last quarter. We achieved revenue of $483 million, non-GAAP earnings per share of $0.55 and strong operating cash flow. For the year, we're raising non-GAAP EPS outlook to a range of $2.42 to $2.44, projecting excellent double-digit growth for the year. We're also raising our operating cash flow targets to approximately $400 million. Brian will provide more financial detail in just a minute. Before proceeding to the company highlights, let me comment on the customer landscape. For semiconductor companies, Q3 was yet another quarter with a relatively weak global economy, particularly in Europe, and with slightly reduced growth in Asia. While this landscape is not really new, the continued pressure quarter after quarter of this economic squeeze is challenging. Simultaneously, though, our customers have a high focus on new technology and aggressive design activity. The result is a relentless demand for advanced tools and IP, areas in which we continue to lead and have a strong track record of excellence. For our customers, high-impact EDA and IP are more differentiating than ever before, making deep collaboration with the right supplier crucial. Synopsys benefits from these trends, and our technology investments and acquisitions are paying off. This is evidenced in the closing of multiple large deals in the quarter, despite significant competitive battles. Superior quality and breadth of our portfolio, as well as the engagements of our highly skilled global support team helps us win the fought-over business. Looking at the continued technology evolution, Synopsys today enables the most advanced designs in the world. Be it design at the most innovative FinFET-transistor-based technology nodes or be it advanced design at more established nodes, customers rely on Synopsys whenever they want differentiation from their competitors. Fundamentally, their differentiation is achieved along the 3 axes of better, sooner and cheaper. By better, we mean chips that are faster and/or lower power and, in most cases, are both. By sooner, we mean earlier time-to-market, which involves every aspect of design, including the verification of hardware and software. And by cheaper, we mean chips that are smaller, denser and achieve higher yield in manufacturing. Needless to say, each of these dimensions competes with the others and really good tools, IP and support materially impact the overall results. This is also why the new type of vertical transistor called FinFET is so important. FinFETs are simultaneously faster, smaller and lower power, but they do require sophisticated tools and IP. Synopsys has taken a strong leadership position in enabling this promising wave of advanced design, and we see excellent adoption as companies are investing more aggressively in this direction than initially forecasted. To date, approximately 90% of 20-nanometer and below tape-outs have used Synopsys implementation, and we're already engaged all the way down to 10-nanometer. This past quarter, we saw the number of designs at 20-/22-nanometer and 14-/16-nanometer increased notably. Except for some specialty approaches, all 14-/16-nanometer designs are 3D FinFET-based, and all key foundries are investing heavily to develop their FinFET processes, promising eager customers about 40% lower power consumption. Synopsys has been investing in FinFET enablement for half a decade, and we have at least a year head start over any competitor. Our complete solution addresses design challenges from the earliest stages of process design, transistor development and characterization, library and memory IP development, digital and analog/mixed-signal design and verification, all the way to complex IP cores and sophisticated global support. By now, we also benefit from production-proven tools and IP, with more than 100 million FinFET chips shipped, thus far, using Synopsys tools. During the quarter, we announced a number of customer and ecosystem partners successes, all the result of multi-year collaborations. TSMC, for example, certified our digital and custom design and verification solution for its 16-nanometer FinFET process. We also delivered a comprehensive design implementation solution for Samsung's leading-edge 14-nanometer FinFET process. And we announced UMC's first qualification tape-out in its 14-nanometer FinFET process, achieved using Synopsys tools. These are just the latest in a growing string of achievements, including the tape-out of Samsung's first 14-nanometer low-power test chip. Samsung chose Synopsys as their FinFET partner because of its successful collaboration history and the comprehensive capabilities throughout our portfolio. Another excellent example is FPGA provider, Achronix, standardizing on IP Compiler and IP Validator and taping out the industry's first commercial FinFET-based SOC using our tools. Now let me turn to verification, where technology leadership is just as important. Today, our digital verification is used in the vast majority of advanced designs, and 19 of the top 20 semiconductor companies use Synopsys circuit simulation. With smaller transistors, and thus more transistors on a chip, the need for massive amounts of verification continues to grow. This is why the quest for still faster simulation is essential to our strategy. In that context, our VCS simulator and ZeBu emulator both have the fastest run times in their category. Growing equally rapidly in importance is the need to simultaneously verify hardware and software. Our combination of emulation, FPGA-based prototyping and virtual prototyping is unique in its breadth and capabilities. This is an area for growth for us, and prototyping, specifically, has been strong for us all year. In the past, customers typically built and assembled complex FPGA boards in-house to complement their chip simulation and accelerate their hardware/software debugging. These efforts are increasingly being outsourced to us, and we're collaborating closely with some of the most advanced design companies in the world in this area. To fully increase the impact of all these verification technologies, we are substantially investing in integration around the Verdi debug system. As you may recall, we acquired Verdi through the acquisition of SpringSoft late last year. It is the gold standard open debug system used broadly across the world. I can report that not only is the product superb, but the integration, while an enormous task, is progressing well. A number of key customers are collaborating closely with us in setting long-term direction. Let me close with an update on our IP products, which continue to thrive and grow. Over the past 10 years, the use of third-party commercial IP has gone from experimental, to periodically used, to mainstream. In parallel, the complexity of our IP has evolved from simple cost-advantaged blocks, to a broad portfolio of all the main interface protocols, to now extremely complex state-of-the-art and rapidly evolving next-generation solutions. In addition, our team has also become extremely proficient in the advanced technologies around FinFETs, and we're heavily engaged in sub-20-nanometer libraries, memories and analog IP. According to Gartner, Synopsys is the largest provider of physical IP, more than double the nearest competitor. The amount of IP that the top 20 semiconductor vendors consume has increased by 5x over the past few years and now represents almost half of our DesignWare IP revenue. Overall, we're the second largest IP provider in the world, with about 1,900 engineers designing commercial IP blocks, giving us the #1 position in interface, embedded memories and analog IP. We estimate that only about 50% of these types of blocks are outsourced today, and we expect this area of our business to continue to yield double-digit growth, driven more -- by more outsourcing as well as additional protocols and titles. In Q3, we released memory blocks for a number of 14-/16-nanometer FinFET processes, realized a key competitive win in interface IP and were chosen as the strategic IP partner by a large U.S. company for 16-nanometer FinFETs. Lastly, we also announced a new low-power IP subsystem for sensors, aimed at the "Internet of things" markets. This is an integrated, pre-verified system that sensor developers can purchase off the shelf rather than developing and assembling each component themselves. In summary, Synopsys continues to demonstrate broad strength and innovation in technology, customer relationships and financial execution. We delivered very solid financial results in the quarter, and as a result, we're raising our non-GAAP earnings per share and operating cash flow guidance for the year. I'll now turn the call over to Brian Beattie.