Aart J. de Geus
Analyst · Mahesh Sanganeria with RBC Capital Markets
Good question. It's actually very much across the board, because it starts with really the design of both the technology, which, by the way, is moving to a very, very small node, 14-, 16-nanometer. And with that, there's a lot of lithography type of issues, but there's also lithography creeping into the place en route by virtue of what's called double-patterning. Secondly, the entire layout space is highly impacted, because the nature of the transistor will change the timing and power calculations. But the layout is also influenced greatly by all the rules that you have to follow to place these things on the chip just right. And when I say rules, we're talking essentially a doubling of rules of 2,000 to 4,000 rules that you have to follow. And then, indirectly, it really impacts, or it will impact, I should say, going forward the entire verification space. Because all the way down to the SPICE level, simulation of the transistor, all the way up to the sheer number of transistors, and therefore, complexity of chip verification from a functional point of view. So it is quite remarkable the breadth of it, but it's also quite rewarding because that is the very, very reason that we can see how much impact this will have on design and on electronics going forward. Then summarizing all of that, it also impacts every one of the building blocks. And again, you can look at the transistor as being literally the smallest atomic building block, all the way to the large pieces of IP that have to be tuned for these technologies. And as I mentioned in the context of an earlier question, we have been working on IP developments, be it in memories or libraries or building blocks, now already for quite a while. And in that sense, I think we are very much in sync with the foundries as they roll out their production-ready solutions.