Leonard Charles Perham
Analyst · Gary Mobley from Benchmark
Thank you, Bev. Welcome, everyone, and thank you for joining us this morning. I'll begin today's call with a review of our major 2012 accomplishments and then discuss our current sales efforts, the ongoing development of our second-generation Bandwidth Engine and as well, the ongoing efforts being put into our future products roadmap. Jim will then review our fourth quarter and full year 2012 financial results prior to opening the call for further questions. Under the heading of 2012 Major Accomplishments, the fourth quarter of 2012 topped off the year during which we achieved a number of major accomplishments as we transition MoSys to be an IP-rich, fabless semiconductor company. I'd like to spend a few minutes reviewing a few of those accomplishments. First, with respect to our first-generation Bandwidth Engine family of integrated circuits, we met a number of quality and reliability goals. The circuit accomplishments included ISO 9001 certification, freezing and spec’ing out all of our back end test flows, completing our qualification testing and starting our QA&R benchmarking. Towards that end in May 2012, we successfully completed high-performance operating life, or HTOL as its known, reliability testing for 1000 hours on 3 separate wafer fab runs with no failures. 1000 hours is the required benchmark for carrier-grade certification. And each 1000 hours under these test conditions is roughly equivalent of 10 years of standard operating life. To further demonstrate Bandwidth Engine's reliability, we took a portion of each of the 3 lots, and continued the testing up to 3000 hours. This material completed and passed the 2000-hour milestone in September 2012, no additional failures, no failures actually, there've never been a failure. And then passed the 3000-hour milestone in November 2012, again with no failures. Successfully passing these benchmarks was a significant achievement, which attest to the quality and reliability of our Bandwidth Engine integrated circuit family. Or said another way, it attests to the very high quality integration of TSMC's excellent process technology and our design, our design criteria. The results of integrating design and process together will give you the very best results product-wise. We vastly exceeded the required statistical quality and reliability benchmarks and successfully achieved carrier-grade certification, allowing us to bring the Bandwidth Engine to market, achieve our first OEM design wins and subsequently release the product into production. Second, we secured our first Bandwidth Engine OEM design wins with lead networking equipment suppliers from multiple system platforms, which will utilize anywhere from 2 to 11 bandwidth engines per line card. We are very excited to be collaborating closely with our OEM partners as they finalize their system-level specifications and advance toward prototype system builds, which are expected to reach full system qualification and initial production release in the second half of this upcoming year. Third, we substantially completed the wind down of our IP business in the third quarter of 2012, having met our performance obligations under the final outstanding IP project agreements, including a technology transfer in support of our March 2012 sale of SerDes technology to Synopsys. This has allowed us to continue to redeploy resources in support of our integrated circuit product efforts and will allow us to further reduce operating expenses in 2013. Fourth, we successfully taped out the second-generation Bandwidth Engine in November 2012. We have already announced the 2 unique products from this family and will soon announce the third, all targeting specific next-generation network equipment, applications and systems design challenges. My fifth point relates to our SerDes technology. Our second-generation Bandwidth Engine will run at I/O speeds up to 15 gigabits per second, making it the fastest serial memory available on the market. Most recently, at DesignCon this week, we demonstrated our advanced 25 gig SerDes technology operating at 100 gigabits across the backplane using 4 lanes at 25 gigabits per second. We're excited about the availability of this leading-edge SerDes technology to be used in our future generations of bandwidth engines and/or other extremely fast integrated circuit products and uniquely fast system requirements and applications. Finally, our sales activity has increased dramatically year-over-year and continues to be at that all-time high. We entered 2013 with a funnel of projects and customer prospects more than double the size of where we were beginning calendar year 2012. This increase was driven by a number of factors, including the increasing market demand for systems that can support aggregate bandwidth of 100 gigabytes per second or more, the proven release and production readiness of Bandwidth Engine, hard work and the strong concentrated effort by our sales, marketing and applications teams, our expanded worldwide sales channel as we added distribution and sales representatives to optimize our sales coverage and provide strong local application support. Since entering 2013, the majority of new sales activity is targeting use of Bandwidth Engine for new systems requiring greater than 200 gigabits per second aggregated bandwidth. We anticipate our sales activity to remain high with our targeted release of Bandwidth Engine 2 for sampling. We already have multiple customers and prospects putting pressure on us for Bandwidth Engine 2 samples. And I am confident we will see a good deal of traction from this new Bandwidth Engine family in the quarters ahead. It's important to note that substantially all of our design wins to date have been in applications where the FPGA is utilized as the packet processing engine. As we enter 2013, we are now seeing considerable interest in using Bandwidth Engine products and systems built around ASICs, SOCs or NPUs being used as the packet processing engines. These systems, in almost every case, are the highest performing systems in a design queue at our prospective customer shops. Now a quick comment about our GigaChip Interface. We recently announced that Renesas Electronics, a leading provider of high-performance ASICs, will support our GigaChip Interface in its networking ASIC business in order to gain the benefits of increased reliability, higher performance and improved efficiency that this open-platform interface can bring designs where serial chip-to-chip interconnects are being utilized. Renesas joins other market-leading GCI adopters and supporters such as Altera, Xilinx, Avago, LSI and others. The GigaChip Interface is an integral part of our Bandwidth Engine integrated circuit architecture, and we look forward to supporting Renesas in its use of GCI. In summary, our sales channel is now well established, and we are satisfied with how it is performing. We have a growing list of prospects in the pipeline and a strong family of opportunities that are moving satisfactory toward a design win status in all of our 3 primary regions, the U.S., China and Japan. From a sales organization perspective, we recently announced that Dave DeMaria has left MoSys after 4-plus years of service. Initially, Dave joined MoSys to direct out IP business, and as we transition toward being a fabless integrated circuit company, we're moving further and further away from his career path, and for that matter, his comfort zone. Prior to MoSys, Dave had a successful career with multiple EDA companies and was recently offered a solid opportunity with a major EDA company that he believed was more in line with his current career ambitions. We wish Dave well in his new endeavor and thank him for his hard work and contributions to MoSys. John Monson will be assuming the majority of Dave's responsibilities. Now turning to our second-generation Bandwidth Engine product family, specifically Bandwidth Engine 2. We taped out BE2, Bandwidth Engine 2, on November 23, after satisfactorily completing extensive logic verification and timing closure analysis. We expect to receive package units back for evaluation and characterization testing starting around mid-March 2013. Subject to meeting the BE2 specification, we expect to ship initial samples by mid-year. As we mentioned earlier, there is early demand for BE2 samples, and we are pushing very hard to get the products back, get the characterization done and get these prototype demands satisfied as quickly as possible. BE2 is a significant evolutionary step beyond BE1 and benefits from several performance enhancements, including access speed that's increasing from 2.75 gig accesses per second, or 1 billion accesses per second, to greater than 4 gig accesses per second. I/O speed is going to be up from 10 gigabits to 15 gigabits per second. And latency, round-trip travel time in and out of our Bandwidth Engine, is going to be reduced from 15 nanoseconds to 12 nanoseconds. In 2012, we announced the first 2 products based on the BE2 architecture. The first MSR620 is optimized for buffering applications up to 384 gigabits per second, and includes burst write and read, and write and broadcast capability. It also accelerates the large packet sizes up to 576 bytes, and has an unprecedented 80% overall bandwidth efficiency which is beyond the capability of currently available standard memory subsystems and alternative serial interface solutions. The second, the MSR720 access device, is optimized for high access rate applications and packet header Processing and is well suited to the requirements of state memory and queuing applications. It also contains memory coherency, which allows back to back read and write to the same memory bank, allowing for higher efficiency through small tables. Additionally, we expect to announce a third BE2-based product shortly. This new member of the family will provide additional computational capabilities to off load repetitive tasks for improved performance and intelligence, and will be targeted for a broad range of look-up statistics and policying applications. At this point, I'd like to take a moment to thank our engineering operations and applications teams for the excellent work throughout 2012, and the many long nights and weekends they worked to meet their deliverable milestones and schedules. The dedication and diligence enables us to achieve a remarkable amount of progress in a short period of time during the past year and has us well-positioned to convert existing opportunities into full-fledged design wins in 2013. With that said, let's take a quick look at what's next on our product roadmap. For now, I'm going to refer to this simply as Generation 3. While I won't get into a lot of specifics at this time, we continue to work on defining the feature set and performance levels of our next generation, which I will refer to Gen3 rather than as Bandwidth Engine 3. Gen3 is an early development and leverages our extensive technology base but will be architecturally different from earlier Bandwidth Engines. In other words, it will solve different problems in the system, and would not be referred to as pin-to-pin compatible. We are collaborating extensively with both customers and partners to complete the definition of Gen3 in the first quarter of this year. We expect this product to be a significant step forward in solving next-generation system-level issues of the highest difficulty level. It will again be both a significant performance upgrade and will include a substantially expanded feature set. At this time, we anticipate first silicon in the first quarter of 2014, and that is a very tight schedule. I look forward to providing more information on Gen3 as our development progresses and as we achieve measurable milestones. Advancements in the com instruments[ph] to watch for in 2013. In closing, I believe our key 2012 accomplishments, numerous engineering and operational achievement and increased design wins and sales activity has set the stage for 2013 to be a pivotal year for MoSys. This year, we should begin to expand our product footprint, gain momentum toward profitability and, in fact, see relief for the first time in meaningful quantities of sales of our integrated circuits. We expect to achieve several important milestones and advancements over the course of the year. To mention just a few to watch out for, we expect the course to be shipping initial BE2 samples. We expect to announce multiple new OEM design wins, including multiple platform wins among our Tier 1 OEM targets. We expect to gain support of BE2 from FPGA vendors as we leverage our ecosystem to secure incrementally more design wins. We look forward to securing additional GCI partnerships with NPU, SOC and ASIC vendors as we did with Renesas, which will broaden our prospective customer base and provide new system-level opportunities for us to pursue. We expect to announce new products such as Bandwidth Engine -- or excuse me, we expect to announce new products such as our Gen3 product that will address additional challenges at the board level of advanced systems and we expect to secure a genuine going forward second source partner. As you can imagine, there are many steps to be taking between now and the achievement of these milestones, but we are pleased with our 2012 successes and confident that 2013 will be no less satisfying and rewarding. Before I hand this to Jim, I'd like to personally thank our staff for their hard work during 2012, all of our customers using Bandwidth Engine to bring the most advanced revolutionary products to the markets they serve, and to our shareholders whose continuing support of our goals and objectives is truly gratifying. With that, I'm going to turn the call over to Jim to discuss our fourth quarter and full year financials. We will then open the call for questions. Thank you very much for your time and attention. Jim?