Ladies and gentlemen, thank you for standing by. Welcome to the ASML First Quarter Results Conference Call on April 16, 2014. Throughout today’s introduction, all participants will be in a listen-only mode. After ASML’s introduction, there will be an opportunity to ask questions. (Operator Instructions) I would now like to turn the conference over to Mr. Craig DeYoung. Please go ahead, sir.

Thank you, Kirsten, and good afternoon and good morning, ladies and gentlemen. This is Craig DeYoung, Vice President of Investor Relations at ASML. Joining me today from our headquarters in Veldhoven in the Netherlands is our CEO, Peter Wennink and our CFO, Wolfgang Nickl. The subject of today’s call is ASML’s first quarter 2014 results. This call is also being broadcast live over the Internet at www.asml.com, and a replay of the call will be available on our website for approximately 90 days. Before we begin, I’d like to caution listeners that comments made by management during this conference call will include forward-looking statements within the meaning of the federal securities laws. These forward-looking statements involve material risks and uncertainties. For a discussion of risk factors, I encourage you to review the Safe Harbor statement contained in today’s press release and presentation found on our website and in our Annual Report on Form 20-F and other documents as filed with the Securities and Exchange Commission. Just as a reminder, the length of the call is 60 minutes as usual. Now, I’d like to turn the call over to Peter Wennink for a brief introduction.

Thank you, Craig. Good afternoon, good morning, ladies and gentlemen, and thank you for attending our first quarter results conference call. Before we begin the Q&A session, Wolfgang and I would like to provide an overview and some commentary on our first quarter results and provide our view of the coming quarters. Wolfgang will start with a review of our first quarter financial performance and will add some comments also on the short-term outlook. I will complete the introduction with some further comments on the current general business environment in which we are working and our future business outlook. Wolfgang, if you will?

Thank you, Peter and welcome everyone. Q1 revenue was in line with our guidance of €1.4 billion and was largely driven by sales to our memory customers, which represented about two-thirds of our systems revenue. Also as anticipated, we have recognized revenue of 1 EUV system during the quarter. ASPs of all tools sold remained constant at about €26 million in the quarter. Service and field option sales accounted for €367 million of revenue. Gross margin came in above guidance at 43.6% helped by a favorable product mix and the contribution of holistic lithography option products. With R&D and SG&A in line with our expectations, gross margin enabled our quarterly earnings to exceed Street expectations. Turning to the balance sheet. We ended Q1 with approximately €3 billion in cash, cash equivalents and short-term investments roughly flat with the prior quarter. During Q1, we bought back 2.3 million shares for our total of about €147 million. This leaves us approximately €553 million available for repurchases for the remainder of this calendar year. This represents about 55% of the €1 billion 2013/14 buyback program announced last year. As a remainder, we will propose to increase our dividend by 15% to €0.61 per ordinary share at our AGM on April 23 next week. This dividend will be payable on May 13 to shareholders of record as of April 29. Our system order backlog at the end of Q1 remained constant quarter-over-quarter at just under €2 billion, excluding EUV. The number of NXT:1970 immersion tools have increased from 14 at the end of December to 24 exiting March. Our system backlog is almost evenly balanced amongst memory, IDM and foundry customers. With that, I would like to turn to our expectation for Q2 and Q3. Let me start with a view at the markets…

Thank you, Wolfgang. Wolfgang pointed out that we are seeing a shift of shipments focus in the coming quarters. Such shifts are natural and common in our industry and are the results of the specific dynamics in these industry segments. So , let’s take a brief moment and zoom out to reflect what we believe are currently that will be most significant trends. First of all, we are seeing the introduction of the 3D gate architecture in logic, specifically used for the 14-nanometer and 16-nanometer FinFET devices. As related to logic specifically, it is important to realize that we are seeing the development of four process nodes in four to five years started with 28-nanometer went to 20-nanometer, 16-nanometer to 14-nanometer and 10-nanometer nodes thereby clearly accelerating the shrink roadmap. These aggressive shrinks are driven by the mobile device makers that have become early technology adopters in their search for performance improvements for smartphones and tablets. However, many of those architecture transitions have just left the stage of development and are being moved into the stage of early often risk based production. Device architecture limitations, complexity and learning curves are challenges that customers need to overcome and it will be a matter of time before they are fully resolved. And we are currently in a phase where reassessment of the timing of the production ramps with the advanced nodes needs to be made against the background of this fastest initial ramp for leading-edge logic production that we have ever seen. In that context, it is logical that we are seeing some adjustments of the rollout of the 20-nanometer, 16-nanometer and 14-nanometer capacity ramps. Secondly, we have witnessed the introduction of the 3D NAND architecture, which are focused on increasing bit density through vertical transistor specking and successor to the current…

Ladies and gentlemen, the operator will instruct you momentarily on the protocol for the Q&A session. But before I hand, I’d like to ask that you kindly limit yourself to one question with one short follow-up if necessary. And this will allow us to get as many callers on as possible. Now, operator, could you please give us the instructions and then the first question, please?

Thank you. (Operator Instructions) Thank you. Our first question comes from Mr. Francois Meunier from Morgan Stanley. Please go ahead.

Yes, thanks for taking my question. Yes, Peter, I’d like to jump on your comments you made earlier about an accelerating shrink roadmap you are seeing at the moment. I’d like to reconcile this with maybe a bit slowing down in the computing cycle at the moment, because like the high end of the smartphone is slowing down in terms of growth, same for PCs we are seeing that for a while actually. So, is it more like – maybe like one of the guys you are trying to move to 20-nanometer and then some of the other guys we see that they are a bit struggling with 20. I am trying to move to 16-nanometer and 14-nanometer FinFET and basically it’s a bit like less investment at the end of the today, because like one of them is winner and still they will don’t spend and then maybe we will see what the winners are going to be? So maybe overall, in terms of super cycle or cycle for spending for logic it’s not as good as maybe people would have been anticipated 12 months or 24 months ago?

Okay. You asked a couple of questions in one question. So let me try to answer this briefly. I think if the core of your question is that you are concerned or asking me the question if we are concerned about the speed of the, let’s say, technology roadmap and execution of it whether that is a concern to us. I would say, no. When you mentioned the 20-nanometer, 16-nanometer and 14-nanometer node, that node we strongly believe still needs about 300,000 wafer starts. The first part of that node and let me say this 20-nanometer node, this is a bit of a strange node has two phases. It has a first Phase, which is really the 20-nanometer node phase and then you have the 16-nanometer, 14-nanometer FinFET. Now, on the first part, the 20-nanometer, we have installed about 70,000 wafer starts response as of now, which by the way happened in about four quarters. If you compare it to the 28-nanometer node, that took about 7 quarters to get to 70,000. So, we are actually looking at the fastest ramp up of a new node we have ever seen. On top of that, people are developing 14-nanometer and 16-nanometer FinFET solutions. They are doing that at the same time. What we are in fact seeing is that I don’t think there is any delay in the shrink roadmaps at all it’s just a matter that people are trying to do it faster and that’s driven by performance improvements in the end devices and by cost. So, this is what we are seeing today. And when we talk about timing adjustment of that capacity ramp, I think is logically if you see those being delayed a bit, a few quarters simply because our customers are trying to do too much at the same time. And I don’t think it is specific to one customer, I think it is the need of the mobile industry that is driving the need for more advanced logic solutions and our customers are just trying to cope with this. And we are dealing with that particular demand. So, nothing has changed. I think it is a few quarters delay what actually is pretty good, technology roadmaps are completely intact. And I think it actually helps us, because if we would have executed at the same speed and slope of the 20-nanometer ramp for also the second phase, which is 14-nanometer, 16-nanometer, then we might have a very meager 2015, because everything would have been chipped in one year, which of course is not possible, but I think it is understandable where we are today.

Okay. So, if revenues from the foundries are kind of trending down and the orders as well, it’s really something which is really short-term in your view basically?

Yes, yes. And from a company point of view, we see very strong demand from DRAM, NAND. So, we actually look at when you look at our guidance for the first, the actuals of Q1 and the guidance for the next two quarters were at 4.5 billion for the first nine months. Last year, we did 5.2, if we don’t say that we shipped four systems in Q4 for EUV, hence you can easily imagine that for ASML, 2014 will be a very good year.

Okay, very good. Thank you, Peter.

Thank you, Francois.

Thank you. Our next question comes from John Pitzer from Credit Suisse. Please go ahead with your question.

Yes. Good afternoon guys. Thanks for letting me ask the question. I guess, Peter, can you help us understand a little bit when you think about the revenue makeup in the September quarter more EUV revenue probably a mix that’s moving slightly away from holistic lithography, can you help me understand how we should think about gross margins in that quarter?

Wolfgang, you want to add to that?

Yes, I can take this, John. As you know, our EUV systems don’t contribute to gross margin at this point. And we also know Investor Day we showed like the last quarter’s 43.6% will impact negatively actually by shipping the 1 system by about 2%. So as you ship more, you start off with more pressure on the system. On the other hand side, we have actually holistic lithography solutions outgrowing the rest of our revenue categories. And as you know as largely software driven where we were having like 80% gross margins. And you have also seen that we have a pretty strong backlog on the 1970C, which jumped up to 24 systems. So, there is a bit more uncertainty in the gross margins, because the mix changes here can impact the gross margin. That’s also by the way a reason why we have started to give a range in the gross margin guidance, but we would think that there could be offsets in Q3 to the second system because 1970s and holistic lithography is contributing strongly.

Yes. And I would like to add to that which I also said in my introductory statement that holistic lithography, we used to position that as a particular solution for logic, but as I said earlier, we will also see now this adoption of holistic litho solutions not only on logic, but also in leading-edge memories and especially DRAM. But also if you go to, for instance, floating-gate NAND leading-edge needs absolutely the full suite of holistic lithography products. So, we see a broad adoption of holistic lithography now across all sectors, which will also help the gross margin.

Perfect, Peter. That’s helpful. And then Peter relative to some of the uncertainty around 16-nanometer and 14-nanometer at the foundries, what’s your expectation now for time to volume ramp of 16 in FinFET. And if it’s let’s say fourth quarter of next year, how many quarters ahead of that do you start to get real certainty. So if you think about when do you think the volume production at FinFET starts and what quarter prior to that would you know for certain people’s demand desires?

Well, we have to look at our production and insulation cycle time, because that’s driving these, because we of course do not have detailed insight into what our customers are doing in their development. So, if we take about 8 to 12 weeks of installation time max before a tool that lands will be put into production, let’s say, one quarter, we have six months of production cycle time. So, we need about nine months warning if this, now they start ramping up we need to start building them machine about nine months earlier.

And so Peter, if the expectation is second half of next year for volume ramp, you should start to see certainty some time late Q3/Q4 of this year, is that how I should think about it?

Yes.

Perfect, thank you.

I mean, if your assumption is indeed let’s say middle of next year or third quarter of next year, then you need to adjust that with about nine months earlier.

Thank you very much.

Thanks.

Thank you. Our next question comes from the Sandeep Deshpande from JPMorgan. Please go ahead with your question.

Yes, hi thanks for the question. Peter, maybe you did talk about this in the introduction, but maybe you can help us understand you have talked about this 500 wafers per day on EUV by the end of the year, at what stage do you think that the customers get confident enough to say well, the tool is now stable enough for us to place orders with ASML for 2016? And I have one follow-up.

Yes. I think when you look at where we are today, we initially provide a capability of 100 wafers per day with a decent availability and a decent availability is about over 50%. That’s what we are doing today, but as I said earlier at around 100 wafers per day. These 100 wafers per day is the result of the first great cycle. To get to 500 wafers per day, we need several great cycles, which are planned throughout the year. I think that will determine, I don’t think we will need to show over a lengthy period of time, 500 wafers per day it is the result after every upgrade cycle that is going to increase the confidence of our customers. For instance, the upgrade cycle that we did just after SPIE for the tools in the field actually gave us the projected results. So if we can keep executing on what we are doing today that means that every – after every upgrade cycle throughout this year the confidence level of customers will go up. And that means that we are currently planning to be at that 500 wafers per day around the end of the year, beginning of next year. But I would think that is my personal expectation that we should have the confidence level higher before we reach that point. So somewhere this year I think customers and the ASML need to sit around the table to talk about the follow-up of the industrialization of EUV.

Thanks Peter. Secondly, if I ask you more macro question I mean if you look at what the market is looking for in terms of semiconductor CapEx this year that this should – semiconductor CapEx should grow this year overall driven to some extent by memory CapEx, but your first quarter orders are showing different trend in terms of memory CapEx as well, so do you think that your own orders will catch up with what market trends expect for 2014 in terms of memory CapEx or do you think that market is wrong at this point on memory CapEx?

If you want to talk about the CapEx Wolfgang…

Yes, I will talk in general about corporate growth yield while market CapEx is flat, I mean Peter already talked in one answer to the first question I believe that I mean we are having a strong year. We are guiding to €4.4 billion for the first nine months and then depending on how the fourth quarter looks like we have a significantly stronger yield than the €5.2 billion. So in general our revenue is up significantly and it’s the industry’s CapEx is flat that we would be kind of independent of that. On the backlog question, yes, the backlog is always dependent on what projects are going on and which customers are placing it and in general our backlog is pretty much flat quarter-over-quarter at €2 billion. The very good quality of backlog it was very, very focused on memory as we ended the quarter and you have indeed seen in our revenue there was about two-thirds of the systems revenue was memory. And you will see that balancing out a bit more now and backlog that we have now is actually almost equally split between the three major segments.

And as you know we talk about that a lot of that the orders and the order backlog when you look at who do we ship to and what projects do we ship to those are projects where we are very well positioned, so customers actually indicate to us much more when they need the machines. So our shipment planning with our customers is in that sense more important than the orders. Once we know that we are designed into that particular project, that new fab, that we know we will get the orders and it just depends like what’s been pointed out on the timing of that one or two, three customers putting the orders in for that one particular project. It doesn’t say anything about their let’s say desire to receive those tolls those – you could say that the orders we said this I think before on earlier goals is the end of an administrative process. It is not so much any indication of the willingness of the customer to put capital forward to make sure that it can fuel the next generation of device shrinks because that’s what they are doing. When you talk about DRAM there is no new capacity being built. The 25% bit growth is simply technology transition that will happen, NAND had the same thing. We have a few big NAND projects, well in particular one that is taking new machines they need to support 40% bit growth which will be about 100,000 wafer starts that needs to happen. So the order patterns could be disconnected from what we call the shipment planning and the shipment patterns.

Understood. Thank you, Peter.

Thank you. Our next question comes from Stephane Houri from Natixis. Please go ahead with your question.

Yes, good afternoon. I have a question about the visibility and the way we should think about Q4, according to you what are the main moving parts we should have in mind on the upside but also on the downside? Thank you.

On the upside, I would say like I have said in – as an answer to an earlier question, we have not detailed monthly or weekly insight into development process and the development progress that certain of our customers have and especially when you talk about leading-edge logic. Now, if they have some breakthroughs, they will pull things in, because they know on my earlier question, I think it was John saying what’s the time that they need? They need about 9 months to 6 months of our production time and then about one quarter of installation and ramp up time. So, if they have breakthroughs, they will come earlier, that is upside. Like I said earlier, we need 300,000 wafer starts for this node, which is, it’s the two phase node, the 20-nanometer and then the 14-nanometer and 16-nanometer FinFET. So, that 300,000 will happen just a matter of when and that’s why I said though the ways that we are seeing fully for two quarters. So that is upside. Downside, well I need to think a bit harder, the logic was basically scrubbed you could say, DRAM is obvious. DRAM market is healthy as there is no overcapacity there. There is no square meters being added. There is a lot of technology. We have the NAND situation, the 3D NAND, which by the way could be upside there is no downside, because if 3D NAND is introduced a bit later, then the 40% bit growth needs to be fueled by capacity additions that will be planar. Well, planar also uses leading-edge immersion tools, but there are much more loaded with the holistic lithography options. So, the average selling price would be a lot higher. So, I would think that’s basically how we look at it. I think we have scrubbed in our internal analysis the logic segment for the, I would say, later ramp up of the 14-nanometer and 16-nanometer node and the others I don’t see a lot of downside. And that’s why Wolfgang said, 2014 looks like to be very solid year.

Right. And just a follow-up on the holistic lithography, you’ve been talking about holistic lithography being adopted also by memory manufacturers. When you have been talking about this €1 billion sales target, did it include this or is it an upside looking three years ahead?

No, it did include that, because when you go to the next generation memory devices, whether it’s the next generation DRAM devices or even when you go another node planar node in NAND, that is challenging from a production point of view and there you need the holistic lithography solutions. So that is included.

Alright, thank you very much.

Thank you. Our next question comes from Andrew Gardiner from Barclays. Please go ahead with your question.

Good afternoon. Thank you very much. Just another one around EUV, I was just wondering whether there has been a change in ton from your customers around the EUV development process over the last quarter or so. Peter, you have highlighted the accelerating shrink and the pressure in the industry and some of the difficulties that some of them are having, but is that causing a change in turn from them where say before they may have said well, we think we can do a bit more with multi-pass patterning, now they are acknowledging that EUV is perhaps even more critical than they had previously showed and how would you therefore characterize the timing of any decision on their part what is the sort of the current level of flexibility they have got in terms of the timing for insertion of 10-nanometer, it sort of keep with the dual development track, it keeps slipping out a little bit or they are giving themselves more flexibility to get what’s so latest on that front? Thank you.

I think it is the latter what you said, I think they are creating more flexibility for themselves to do EUV introduction. And that will be driven by, let’s say, a certain level of wafer per day productivity, which is driven by power and availability of another tool. That will be the point where that will be the main focus. But you are correct I think if you which by the way the issue that we are currently seeing with our potential delays I would say in shipment pattern for leading edge logic is driven by the fact that I need to remind you all that by the fact that this roadmap capacity ramp was the most aggressive that we have ever seen. So we are seeing just adjustment of the timing of this ramp, which brings it back to I would say more normal patterns. So, this is the main reason why we have to adjust, let’s say, the initial planning that we had, but on EUV, you are absolutely correct, I mean what we notice and what we hear from all the customers is that the challenges with multi-pass patterning, R&D is very, very high. And that’s one of the main reasons why they want to introduce EUV is not so much because of cost. The cost impact will be limited we talk in logic, for instance, about the few layers, one or two layers, but it is more about the process simplification, it makes the process more simple. And that’s the main focus that our customers are currently having and that of course helps. So, when we reach those, let’s say, 500 wafers per day targets and we are getting close to it, now I am pretty convinced that those customers will make those choices, because the benefits are clear.

Understood. And just a very quick follow-up if I may, you have shifted the focus of the EUV metrics from power and wafers per hour to wafers per day over the last quarter or so. The prior targets that you had set say 70 wafers per hour during the back half of this year, 125 wafers per hour next year in terms of the peak throughput, are those still sort of intact and analogous to the wafer per day targets that you are now referring to or have things changed?

No, they have not changed. I mean, 70 wafers per day, we need to show the capability of 70 wafers, sort of 70 wafers per hour by the end of the year and our capability to 125 wafers per hour in 2015. And that is because customers for the initial start of their risk production don’t need that, but they would really like to see that capability is ultimately there. So, that has not changed.

Thanks very much.

Thank you. Our next question comes from Kai Korschelt from Deutsche Bank. Please go ahead with your question.

Yes, good afternoon. Thanks for taking my question. I have two. The first one was maybe to simplify the sort of push-outs on 16-nanometer and 14-nanometers compared maybe to the overly aggressive roadmaps. I mean, could this potentially mean that also the 10-nanometer rollout maybe somewhat later over the ramps, somewhat later which would in turn then give you more time to execute on EUV roadmap at least compare to maybe what you thought six months ago? That’s my first question. And then I have a follow-up please. Thank you.

Yes. I don’t think there is going to be any delay it is not a follow on. I think what we are currently seeing is that the 16 sorry – 10-nanometer is needed in the course of 2016/17. So we have still more than two years we have left for the 14-nanometer and 16-nanometer rollout, which I think is sufficient time and as a matter of fact, it looks like the normal Moore’s Law heartbeat. So, I don’t think that has any impact, but what we are seeing that’s the intensity with which customers do R&D of 10-nanometer, that is going up and that’s why there is so much interest for no EUV. And I don’t think it has a major impact on the timing of the introductions.

Okay, thanks. And then maybe a brief follow-up on NAND, so I think you previously said 3D versus 2D, that debate doesn’t really impact the sort of lithography content per wafer, but I think you earlier said you are now getting a bit more comfortable with sort of two different scenarios. And I am just wondering so which, if you could maybe be a bit more specific what do you think now if you include the higher software and holistic litho content of one versus the other, what do you think roughly is the litho value in total terms difference between 3D and 2D? Thank you.

Yes. I think that the litho difference is a bit difficult to quantify for the following reason. When you say we do a 3D, you could probably go for the NXT:1965 which is a let’s say a somewhat lower priced tool, which is more cost effective, but it has a lower throughout. So, when you say you go to 2D, you need the 1970C with the holistic litho options on there, but it has a higher throughout. So you need fewer of them. I would think as a gut feel that it doesn’t make a huge difference, plus it is important, because it means that the composition of what we need to deliver is of course different. It also means from a production planning point of view, it’s a bit different. And from an ASP point of view, it is also different that 2D requires higher ASP tools, but also less because of the 1970C is a higher product, it’s a higher product revenue tool, it’s 10% to 15% more productive. And that gives you an indication of the number of tools given the fact that the wafers out requirement, is probably the same that the number of tools on 2D might be less than on 3D.

We were to see some sort of ramp up problems or issues with 3D or qualifications then that would be good for you?

Well, yes, it would be good for average selling price as you would probably sell fewer tools. So, I think from a litho point of view, I don’t think it makes a huge difference from a sales point of view, but from a margin point of view clearly.

Okay, thank you very much.

Thank you. Our next question comes from Mehdi Hosseini from SIG. Please go ahead with your question.

Yes, thanks for taking my question. Can you help us understand how the economics like wafer – ASP per wafer for your customers’ customer are changing as we go into 20-nanometer, 16-nanometer and 14-nanometer? And how those changes in economics are compared to previous nodes like when we transition from 45-nanometer to 35-nanometer? And the reason I am asking is given the fact that there is more multi-patterning at and below 20-nanometer, I am just wondering if those additional cars are also having an adverse impact? And I do have a follow-up question.

Yes. I think it’s a very good question, Mehdi. I think in the general economics are not favorable for our customers when you go to 20-nanometer, 16-nanometer and 14-nanometer. I think the cost per wafer from a lithography point of view will go up, there is no discussion there. And in the sense you could say that is a bit different from the previous nodes where we were still able to fall, let’s say, the cost per wafer reduction roadmap that they had. Now, you need to realize that, that I would say that 20-nanometer, 16-nanometer and 14-nanometer node is kind of a bridge node from a lithography point of view. I mean, we are about two years late with EUV. So, clearly, there is these cost per wafer economics are being impacted by the fact that we have to do so much of pass patterning, not only I think from a CapEx point of view, but probably also from a yield point of view. And that’s why the focus of customers is on introduction our EUV in any case at 10. And that is the game changer again or you could say that’s the change to bring us back on the cost per function or cost per wafer roadmap as we originally planned. And of course, we are trying to help the customers with this economic issue on the cost per wafer by increasing the throughput, the NXT:1970C has a record throughput with the capability to give our customers maximum, let’s say, control over their process, the holistic lithography product portfolio. So yield management plus productivity is something that we have added to our product portfolio to compensate for what is obvious increase in the cost per wafer which can only come down after we have introduced EUV.

Got it. And then the follow-up has to do with the EUV, given your target of 500 wafers per day by 2016 how does that change or can you provide us an update on the total number of EUV that you will be able to ship in ‘16 and ‘17?

Yes. We have said that based on these targets that we talked about we still believe that the capacity that we need to put in place in 2015 is about 12 to 15 units, which with the further successful rollout of EUV, we will have to double in 2016 and double again in 2017. So that statement is still valid. We said that before that’s not going to change.

Got it. Thanks so much.

Thank you. Our next question comes from Timothy Arcuri from Cowen and Company. Please go ahead with your question.

Hi, thanks. Peter, I had a question on the 3350, you are building some 3350s and I think the idea was that you might be able to ship a few of them this year and now it sounds like you have achieved some of the milestones for at least development work. So, can we expect to see follow-on orders and shipments for the 3350 before the end of the year? I would think that we would see follow-on orders based upon what you previously said for some 3350s before year end?

That’s clearly our target, Tim. It’s – we do not spot the production of these systems if we do not think there is a - I would say home for those systems. And if there is a home for those systems we need orders. So I think it’s a fair assumption.

Okay great. And then can you talk a little bit about Holistic Litho, the attach rate looks very high you have – I think you have previously said that you are going to do like €500 million to €600 million this year in Holistic Litho, is this still the case and how much of that is actual hardware versus software. And that – and I ask that because that’s the piece that ultimately gets taken out of the pocket of other companies selling hardware as well? Thanks.

Yes, this is Wolfgang. Yes, the ramp there is completely intact. We did just on the €500 million last year and we are going to get to over €1 billion by 2017. And this year is going to be greater than last year. And I would think that it’s probably 75% software content, 80% software content and the rest is hardware content, which comes from the YieldStar metrology tool that’s included there and the blended gross margin is very, very healthy about 80% for that business.

Which is normal for software, so.

Yes, software is higher and then the yields are a little bit lower but blended 80%.

Blended 80%, okay. Thank you so much.

Thank you. Our next question comes from Gareth Jenkins from UBS. Please go ahead with your question.

Yes. Thanks very much. It’s a follow-up on an earlier question. I just wondered whether you could talk about the number of exposures if you were to do 10-nanometers in the option where you don’t use the EUV, would it be how many were sort of multiples of exposure that you would have to do with immersion. And then I have a follow-up just on EUV…?

Yes, I think the number of exposures, it depends a bit on the architectures of our customers, but in general you could say that in a critical layer on 10-nanometer that there was normally a 2D layer that has to turn into a 3D layer which means one let’s say an EUV layer would then be replaced by two or three immersion layers and with every layer needs multi passes. So a good value from seven to nine immersion passes for that one layer, which then of course if you have a pool they can do two things. If you have this multi passed 3D immersion design for the critical layer which would like I said seven to nine passes, if you would replace that with EUV then you could – and you would not change your architecture, just use the 3-D architecture but then just replace multiple immersion passes with one EUV pass, you can bring it down to two or three EUV passes. That’s one solution. You can also say you are not going have a different design which actually takes benefit of the full EUV capability which actually brings the exposure down to one pass which is the only EUV pass. So you can see how the economics then quickly turn in favor of EUV. But clearly that’s why customers are very interested in us showing the capability of 70 and 120 wafers per hour. Once you are at that productivity level then clearly the economics of the EUV kick in and also gives them a lot of simplicity back because as you can imagine a 3D multi-passed immersion layer is highly complex.

Great and I just want to thank you for that Peter. Just wonder whether would you talk about the EUV developments that you have worked on through the course of this year, can you give us an update on where we are out on the pilot for example and some of the things that you are working on in the industrialization process that we can measure you by?

Yes, I think we have – what we have done last year is to improve the source development whereby we showed the capability of 70 watts which was actually attached to 3100 source – which was 3100 source which basically we then copy the architecture on to the 3300 source which also had a different architecture called MOPA PrePulse. Now so we have MOPA PrePulse now on the 3300 which are the tools that are being shipped to the customer connected to the scanner whereby we have done the first round of upgrades bringing us the level of power and availability that at least gives our customers the requirements for the current R&D development, so in summary bringing the new MOPA PrePulse architecture life on the 3300 source connected to the 3300 scanner which is going to be the scanner being used by our customers for the initial risk production on 10-nanometer. That is what we have achieved for the first three to four months of this year. And that is actually running now I would say well at the customer size, where the customers are now asking us to make sure that we can execute as well on the next couple of upgrades as we did on the first one.

Thank you. Our next question comes from Sumant Wahi from Redburn. Please go ahead with a question.

Hi, gentlemen, good afternoon. Thanks for squeezing me in. My question is actually around the gross margin which you reported for this quarter and probably going forward. Could you possibly kind of give us an idea of how this gross margin gets split out in terms of what has been the effect of Cymer being internalized within this gross margin and how much did – is lithography or Holistic Lithography benefiting the gross margin as such right now? And I have a follow up.

Yes, I mean I will give you a general answer on that. I mean like we said the mix greatly impacts the gross margin just by the fact that we – and we had it earlier on the call Holistic Lithography is greatly accretive as increases as a percent of the revenue and EUV right now is dilutive that will change over the next couple of years. I think the Cymer effect you see over the longer run, the Cymer margin right now are included in the first 11 systems which are very low because we had put the second source in there. But I don’t think we will see any short-term variation that relates to Cymer the short-term variation when we come from the mix of revenue.

But shouldn’t Cymer internalization in the NXT tools have already benefited the company’s margins…

A little bit, I mean it also helps I mean I might add I mean the Cymer service business for instance. The lithos business there is a pretty solid business and that contributes gross margins that are also above the corporate average. But it is not yet another revenue category that helps with gross margin.

Okay. And in fact Cymer is now an integral part of ASML and we are not splitting out our gross margins in the – our different business units. So you just have to live going forward with one gross margin for the company.

Okay. And I guess may this one has been asked in a way as well, but I am just slightly confused about the push out of revenue which was guide about to – I suppose if I do the calculations right it’s about €300 odd million which is being pushed out from Q2, Q3. I am just wondering is there any possibility of you coming back next quarter and saying well what they got their 14-nanometer, 15- nanometer breakthrough and hence we are pulling it back and could this actually feature in Q4 or do we – should we just be thinking about overall hurt on our full year revenues with this expectations with this particular figure?

Well, I think somebody asked that question, could there be upside, well the only upside I could see is that customers have breakthroughs which we are of course not very close to and when they need to take account of the nine months lead time and they might come in early, it might come in a bit later but that could indeed happen. With respect you said the push out of €300 million I calculate…

It was €100 million.

It was about €100 million from Q2 because we never guided Q3, so it’s about €100 million, so which is about 3% to 4% of what we guided so that’s not significant, it’s a few machines but we just tell what it is.

Okay, I guess sorry but I guess my confusion comes from the fact that we were assuming a bit of the 14-nanometer, 16-nanometer revenue coming through in the second half of this year whereas the question previously which was asked was if the volume production comes into the second half of next year or maybe I got that wrong, the nine months ahead of that would imply Q4, Q1 orders?

Yes, those assumptions when it starts the production ramp starts in the middle of next year then they need to calculate back and then they need to get shipments in Q4, yes.

Okay, Q4.

That’s under that assumption.

Alright, thank you very much. I understand.

Thank you. Our next question comes from the Srini Sundar from Summit Research. Please go ahead with your question.

Hi, thanks for taking the question. My first question is why is your 2014 NAND guidance significantly better than two of the memory guys who have 35% and 37% versus your 45%?

Well, NAND, good growth, it’s around 40%. I mean, when you talked about customers, we don’t have any other numbers. If you talk about DRAM, DRAM is probably more like 25% to 27%. So what are you talking about?

Right. On NAND, the customers have guided to 35% and 37% whereas you are guiding to 45%, so I was just wondering where the 8% odd came from?

Well, we said 40%, which is basically is blended amalgamated number of the customers that we talked to and we are happy to talk to all our NAND customers. So it’s kind of a blended number. So 30%, 37% might be a number that somebody throws out and why the 41% or 42% that somebody else throws out we said 40% to 45%.

The presentation source shows mid 45% by the way. Your presentation that was put on the web shows, that’s why I asked the question.

It’s probably 40%.

Okay.

So, I said it also in the introductory statements that it is 40%.

Okay. My other question….

Sorry. Just to clarify that for the others, if you go on Page 16, it shows only 40%.

Okay, thanks. I mean, let’s make that a clarification. It is about 40%.

Okay, thank you. On EUV, how many tools in your estimate are required for the 10-nanometer logic quals and for the sub 20-nanometers across all the customers? What do you think is the size of the EUV revenues from all the quals that are happening?

Yes. I think what will be (indiscernible) is using our capacity that would actually need our capacity of 12 to 15 units in 2015. So if you take the 10-nanometer logic introduction, early introduction of the, let’s say, 1x high DRAM and there will be customers, let’s say, listen we need to prepare our production learning for 7 nanometers, then will have onesies or twosies that we will sell. We think we will be between 12 and 15 units for next year.

Thank you very much.

Thank you. Our next question comes from Weston Twigg from Pacific Crest Securities. Please go ahead with your question.

Hi, thanks. Just two questions. One, the first one, just was wondering if you could give us a little bit more idea on the 14-nanometer push-out regarding technology challenges, you said maybe customers could have a breakthrough to get upside, but it sounds like you have high conviction that demand does pick up within the next few quarters. I am just wondering how severe the technology challenges that you are seeing are at that 16-nanometer, 14-nanometer FinFET node?

I mean, we don’t see that to the level that would make us expert on subject, those are the customers, but we see the behavior where of course customer say hey, this could be a few quarters late. So this is what we are reporting to you that we actually see that has a result, but I think in general what we are seeing is a innovating desire and push from our customers to keep shrinking. And that means that if you look at what they tell us and we look at certain assumptions on the growth of the end-markets, the 300,000 wafer starts for this node, which is this two-phase node, 20-nanometer and let’s say the FinFET node is a very realistic number. And whether that happens, let’s say in 20 months or in 26 months, it doesn’t really matter. I mean, so this is where our confidence comes from that we believe in the discussion that we have with our customers that they are going to solve any issue that they currently have, which I believe is largely driven by the fact that they are speeding the shrink roadmap to such a point where they are putting so much strain on their own resources and that it is inevitable that’s from time-to-time you will see some of those push-outs, which basically brings this node ramp back to what it should be. So we have seen, I repeat it again, the beginning of this node was the fastest ramp we have ever seen. It just goes back to normal heartbeat.

I see. That’s helpful. The other quick question I had was just on 3D NAND you discussed that you are engaged with some customers, I am wondering how many customers are actively working on 3D NAND with you right now?

All of them. I think 3D NAND is just an architectural choice that is happening throughout the whole industry.

Okay. And have you shipped tools to all of the customers for 3D NAND development that you know of?

We don’t know what they do in their development fabs, but we do know what they ask us to ship. And that clearly indicates that they are all planning at a certain level, at certain model, day and time and I cannot be specific about the customers of course, the introduction of a vertical NAND solution.

Perfect, very helpful. Thank you.

Well, actually, let me jump in here, if you don’t mind that, because we only have time for one last question. If you were unable to get through on the call, feel free to give Investor Relations department a call and we will get back to you as quickly as we possibly can. So with that, operator, I think we have the last question.

Thank you, sir. Our final question comes from Amit Harchandani from Citigroup. Please go ahead.

Good afternoon, gentlemen. Amit Harchandani from Citigroup and thanks for absolutely squeezing me in. Just one quick question, if I look from 2014 towards 2015 and we talk about 2014 being a good year for ASML and clearly with 2015 we are talking about 12 to 15 EUV tools coming through, I mean, what would be the different drivers that would – that you could think of for the puts and takes? What kind of growth can we expect going from ‘14 to ‘15? I understand this is a hypothetical question, but just to know your thoughts of what could be the moving parts where you have seen more confidence than the others? Thank you.

Well, I think it’s a good question, but of course we aren’t going to give you any guidance on 2015 if we know they will do even guide on the fourth quarter of this year, but it’s – but the general comment I would like to make, I mean we have been talking a lot about what people call push outs, I would call it, going back to the regular Moore’s Law heartbeat, the regular ramp, because this two-phase 20-nanometer FinFET ramp was the fastest we have ever seen. Now if you see an adjustment of that timing which is good, because it would not be an adjustment, everything would have been pushed and pulled into 2014, yes, which actually would mean that that nodes would have been the fastest ramp, then the 300,000 wafer start would have been installed, let’s say, first half of 2015. Now, that if we now go back to a more normal pattern of ramp up, then 2015 would just see the result of the rollout of the FinFET solutions together with the mobile rollout of I think the capacity additions that we need to see in NAND and the further technology transitions in DRAM. So I think what we are seeing today levels out, yes, let’s say the capacity ramp over the years 2014 and not as the expectation was the emphasis on 2014 only. I think that is qualitative answer, but I cannot help you more than with this.

Appreciate it. Thank you.

Thanks everybody. To finish the call, I would like to thank you again formally on behalf of the ASML’s board of management for joining us today. And Kirsten, if you could formally conclude the call, we would appreciate it. Thanks.

Ladies and gentlemen, this concludes the ASML first quarter 2014 results conference call. Thanks for participating. You may now disconnect.