Peter Th. F. M. Wennink
Analyst · JPMorgan
Thank you, Wolfgang. As Wolfgang highlighted, we've seen a significant shift in our backlog in favor of the memory sector, which will help drive our first half revenues. This year, we will see the continued node transitions in NAND Flash and DRAM, as well as the addition of NAND Flash capacity, including an initial phase of 3D NAND manufacturing capacity build. Based upon customer interactions and research data, we expect low to mid 40% bid demand growth for NAND, and between 20% and 30% demand growth in DRAM, driven largely by the mobile application space. First half, we'll see the foundry logic sector taking some time to absorb the rapid 20-nanometer capacity build that we witnessed in the second half 2013, before we expected 16- to 14-nanometer node ramp will start in the second half of this year. Like Wolfgang said, the 14-nanometer microprocessor manufacturing ramp started late 2013 and will continue throughout 2014. The industry has entered a very interesting time as the challenges of device designed and performance have in turn, created significant manufacturing and cost challenges in pursuit of continued cost-effective strength. In past conference calls, we have discussed our company strategy to address these issues, which is based upon execution around a very significant R&D investment for technology leadership. I think it's important to repeat 4 key areas of our strategy in the context of today's environment. First of all, it's the continued significant performance improvement of our current, dry and immersion scanner architectures, which enabled the most cost-effective leading-edge imaging solutions, which will help our customers to address the imaging complexity involved in multipass patterning strategies at the current and the future of those nodes. Secondly, the buildup of our application products or our Holistic Litho portfolio, enabling and differentiating further our dry and immersion products in support of sub-20-nanometer process control challenges, many of them related to the aforementioned multipass patterning strategies. Thirdly, the introduction of EUV, the next-generation litho technology, the delivery of which will enable the continuation of Moore's Law, by providing large cost reductions, device power savings and further device performance improvements. And fourth, the creation of a strong and highly competent R&D infrastructure to react to any relevant request from the industry, such as the potential 450 millimeter wafer size insertion. The execution of this strategy enables us to support any short and long-term lithography need of the industry. This becomes particularly evident when we look at the challenges of our customers to address the 10-nanometer logic node transition. In order to control risk, customers may decide to initially focus on the use of our most advanced NXT:1970 immersion scanner, enabling execution of their complexed multi-patterning strategies supported by the complete suite of Holistic Litho products for maximum process optimization, thereby making this technology the current process of record. As mentioned previously, the progress we have made in the development of leading edge immersion technology has culminated into our new NXT:1970 immersion system. This machine combines world leading performance of 250 wafers per hour with overlay achievements of less than 2 nanometer, which, when matched with a suite of application products, enables aggressive multi-patterning strategies, which our leading-edge logic device customers can safely choose to plan their sub-20-nanometer designs. The NXT:1970 has seen widespread and quick adoption in recognition of its value, and we shipped 5 tools in the 3-month period post-introduction and have built a 14-system backlog with a value just over EUR 700 million. The value of this system to our customers is translated into a very strong average selling prices, currently and slightly above EUR 50 million while maintaining very healthy margins. The adoption of our application products, again key to the performance at the 20-nanometer and below, is expected to grow again in 2014, likely to a level between EUR 500 million and EUR 600 million. While it is clear that the performance of our newest immersion systems help our logic customers, we also see significant demand for these systems from our memory customers. The complexity of 3D NAND also requires best available overlay and focus capability, and will furthermore require a significant number of immersion systems, which we are seeing now as 3D NAND chip manufacturing volume start to grow. We are very satisfied with the acceptance of our NXT:1970 as the most advanced lithography solution in the industry and as a viable choice for the 10- nanometer logic node. However, we realized, together with our customers, that the continuation of further shrink, therefore, Moore's Law, ultimately and inevitably depends on the introduction of EUV. We are therefore working very closely with selected customers on the industrialization of our EUV technology, which we will very likely adopt when their economic targets for initial insertion of these more cost-effective solutions are actually met, thereby optimally addressing the economic and cost challenges of this node. Regarding EUV, we're happy to report good progress. First 3 of 11 NXE:3300B scanners have been shipped. In the last 2 weeks, the fourth -- a fourth system has been signed off and is in the process of shipping, while 7 additional systems are in state of integration. In the fourth quarter, progress has been shown. First, source code to all systems, enabling the increase of output power by 40%, showing up to 50 wafer per hour capability in our factory. Second, source of time and cost of ownership improvements through institute cleaning technology of the EUV mirror in the stores. Third, defect management through the development and use of chemicals on the photo maps. Despite our continued good progress, we have currently not yet reached a stage of industrialization, whereby our customers can confidently assign their critical layers for their most advanced future nodes to EUV. However, the progress that we see gives us full confidence that we will reach that stage before our customers put these nodes into full volume production. We therefore remain fully engaged in EUV insertion planning discussions with our customers, some of which at this point, have already qualified EUV for imaging at the 10-nanometer foundry logic node. Going forward, with the benefits of EUV clearly understood, insertion decisions will be based on the economics of EUV, driven by productivity, stability and cost of ownership improvements, in turn driving layer-by-layer insertion when these improvements become available. With that, we would be happy to take your questions.