Aart de Geus
Analyst · Needham & Company
Well, I think in general, TSMC specifically, has put a high degree of emphasis and hard work on 28-nanometer, and I think they've done very well with that. At the same time, it is also clear that when you go to these smaller and smaller geometries, the tolerances of the technology become larger versus the size of the device. Well those very tolerances reflect themself directly inside of the design. And so what we have now clearly demonstrated, is that yield is about, I would say, 1/2 to 2/3 the results of design technology and about 1/2 to 1/3 the result of actually, manufacturing prowess. Well that's a very important statement because that says that the design community needs to become much more yield sensitive. Now if you compare that to let's say 10 years ago, where most people did designs and then they would send it to the fab and the fab would execute it and end of story. Well today, you have to really tune your design for yields optimization. And actually we have some very exciting tools that are doing well one is called, Yield Explorer that allows our users, the design community to find yield issues much more rapidly. Because there's one more component, it's not just the absolute number of how good is the yield, it is how good is the yield over time. Meaning when you start in a new node, it tends to be not so great and then you tune and tune, and tune, both on the fab side as well as on the design side, and then the yields moves up. That's called the yield ramp. And so the faster you ramp, the faster your chips become cheaper. And so it's in that context that Yield Explorer is doing very well. And actually, just in the last couple of days, I've had interactions with foundries that are optimizing and where Yield Explorer has been able to find some, essentially, bad situations in the design that immediately helped the resulting yield. So I think it's an opportunity for us, the design world and the manufacturing world are no longer disconnected.