Good afternoon. I am pleased to report that in Q2, we again delivered solid results with in-line revenue, good expense management, slightly above target earnings and strong cash generation. Moreover, we made good progress increasing our total available market for long-term growth. Over the past several years, we have been executing on all fronts. R&D investment, global customer support and targeted acquisitions, all resulting in very solid financials, as we have emerged as a clear industry leader. Let me first summarize last quarter's financial results. We met or exceeded all of our Q2 targets. We delivered non-GAAP earnings per share of $0.41, with revenue of $338 million. We carefully managed expenses and are on track to meet our ops margin target of 24% for the year, and we're heading towards meeting or beating our initial revenue, EPS and cash flow objectives for the year. Before reporting on our strategy and execution, let me address the economic landscape that our customers are navigating and its impact on EDA [electronic design automation] and Synopsys. While the worldwide economy is gradually recovering, the semiconductor industry has experienced a rapid increase in demand. Companies are ramping up chip production as quickly as possible. Most of our customers have reported solid results, are seeing a strong six-month outlook, and in many cases, are reporting capacity shortages. Simultaneously, they do remain cautious, as there is an ongoing focus on cost throughout the supply chain. Semiconductor executives continue to reassess every part of their business and are moving resources to the most value-added functions and projects. Although I would continue to characterize the EDA market as challenging overall, Synopsys is well-positioned to help customers, both in terms of cost and productivity focus and also with the need to accelerate innovation and differentiation. Indeed, we continue to be the supplier of choice for many of these companies. And again in Q2, several customers chose us as their primary EDA partner, including Yamaha, a leader in audio and graphics chips. As companies look at increased differentiation though, through a combination of hardware and software, they find Synopsys a ready partner to drive this emerging quest forward. Having said that, the implications of the customer landscape on near term EDA growth are mixed. On the challenging side of the ledger, we see cautious buyers, continued customer consolidation, considerable competitive pressures and core EDA budgets that are not growing. On the positive side however, the adoption of 40-nanometer, 45-nanometer and below design nodes is accelerating. IP reuse-based design methodologies are growing, hardware/software co-verification is becoming a necessity and integrated design flows are demonstrating substantial productivity benefit. For Synopsys, this is good news. We continue to lead the industry in advance designs all the way below 28-nanometer, and our highly-tuned product portfolio can handle the most difficult complexity challenges. Our IP is very strong. The interest in system solution is rapidly growing and our R&D engine continues to keep us in a strong technology position. So notwithstanding the overall market challenges, we have been able to hold average run rates roughly flat and are focusing on near-term growth efforts towards the IP and systems adjacencies. Consequently, our strategy remains unchanged: One, maintain our technology momentum, increase our efficiency and expand our core EDA leadership; two, broaden our core EDA TAM by fielding adjacent products and capabilities; three, expand our TAM beyond core EDA by aggressively driving the emerging IP and systems space. Let me begin with some highlights around core EDA. Our R&D investments continue to pay off. Not only have we made outstanding progress in providing leading solutions for the most advanced nodes, but we're also innovating in-house to optimize the design flows for substantial productivity improvements. Indeed, for the second year in a row, our Galaxy Design platform has won the EDN Magazine Innovation Award. The driver this year was IC Validator, which integrates physical verification with IC Compiler physical design. With our In-Design technology, designers can now perform physical verification checks and repairs during design, thereby reducing late stage surprises and unnecessary iterations. Feedback from customers is strongly positive and adoption is progressing ahead of expectations. Driven by the integration of IC Validator and IC Compiler, one of the largest semiconductor companies in the world selected Synopsys to displace the incumbent. In verification, our VCS simulator holds large lead in customer usage for advance designs. In addition, we're increasingly beating the competition in more mature process nodes, with two competitive displacements in Q2, based primarily on better performance and memory efficiency. In manufacturing, Renesas Adopts [Renesas Adopts Proteus OPC], our optical proximity correction for advanced 28-nanometer developments. By providing customers the best combination of accuracy and run-time performance, we can enable a shorter, more cost-effective development cycle. Now to efforts to broaden our core EDA TAM. Our most notable focus has been the rapid maturing of Custom Designer, our analog/mixed-signal design tool. We now have not only a complete solution but also compelling differentiation, in terms of ease of use and open architecture and tight integration with other Synopsys tools. The quality and size of engagement opportunities have steadily increased, yielding several customer wins, including a competitive displacement at a company designing advanced network IPs. In addition, from reprocess design kits (sic) [process design kits] or PDK support is growing for processes across the board from 180, all the way to 28-nanometer. Another new product, Yield Explorer, is also generating notable customer interest, as it accelerates yield ramp by diagnosing yield issues during design, where major semiconductor companies successfully use Yield Explorer for 90-nanometer and 40-nanometer design, and is now broadly deploying the solution through their organization. And finally, let me address our efforts beyond the core, up into the IP and systems domain. This area is growing well, both organically and through acquisitions. Our strategic vision and investments of the last 10 years are coming together at exactly the right time. Today, IP and systems represent approximately 13% of our total revenue and is rapidly approaching $200 million in annual business for us. IP had a very strong Q2, with many large semiconductor and systems firms making purchases. The drivers for this success are the following: Major [ph] buy decisions have accelerated, as customers stringently evaluates their cost structures and refocus their engineering on differentiation; in addition, post-recession time to market pressures have increased, forcing customers to quickly move to the new connectivity standards. Since Synopsys not only provides a broad catalog of these IP titles, but also has a strong reputation for quality and performance, we're the natural choice to partner in this area. One of those titles is USB 3.0, also called SuperSpeed USB, a rapidly growing new standards that provide 10x speed up over the previous generation. Synopsys was the first IP vendor to pass compliance and certification testing for SuperSpeed USB, and our product won the EDA Innovation Award for IP this year. We are also seeing strong business in areas such as HDMI and DDR, on both the analog and digital side. During the quarter, we announced our new DDR multi-PHY, which supports multiple standards on a single physical core without sacrificing power or area. Our development importing engines are cranking with dozens of new versions released each quarter. Synopsys is the second largest IP provider in the world, second only to ARM, and is the number one supplier of interface and analog IP. Complementary to our IP focus is our systems strategy. In Q2, we bolstered our already strong offering in algorithmic design and virtual prototyping by closing acquisitions of VaST, a leading supplier of virtual prototypes for automotive and consumer; and CoWare, the industry's broadest and largest supplier of system level tools. The integration of both companies is proceeding with good customer feedback and engagements. We've also further strengthened our portfolio with the introduction of our next-generation rapid prototyping. The new system doubled the size of designs that can be prototyped on a single board, while increasing prototyping speeds by 30%. Customer demand is very high, and we're selling these systems as fast as we can build them. Synopsys has the most comprehensive set of solutions in the IP and systems space and is the clear leader in enabling our customers to accelerate software development, raise the level of design abstraction for efficient chip design and have access to a rich set of IP and model. In summary, Q2 was a solid quarter for Synopsys. We maintained average run rates and made progress in our broadened core EDA TAM. We executed particularly well in IP. We substantially solidified our emerging systems offering. And last but not least, we delivered strong financial results and have a balance sheet that gives us many opportunities going forward. With that, I'll turn the call over to Brian Beattie.