Andrew Pease
Analyst · ROTH Capital. Your question please
Our momentum in the marketplace has increased significantly during the last three months, and we expect that trend to continue. While its easy to describe our activities into display bridge and smart connectivity markets. The direction and evolutionary path of sensor processing markets are more difficult to articulate. To clarify our position and outlook for these markets, we prepared a special slide presentation for this conference call. As we noted in the press release and Ralph mentioned earlier, you can access the webcast with slides at the event section at ir.quicklogic.com. Please join me now for the presentation. In October 2013, we announced our entry into the sensor processing market with our first silicon platform based on our patent pending Flexible Fusion Engine or FFE. During the 60 months of followed, we built out a complete sensor processing system solution. The cornerstones of this solution include a clear silicon platform roadmap, a growing library of world-class sensor algorithms, a suite of development tools and reference designs, and the assurance of easy system integration provided by our sensor QVL and ecosystem partnerships. Our cornerstone strategy has resonated well with our customers and enabled us to nearly double the number of design engagements during the last three months. More importantly, we’re seeing an increased flow of design wins from these engagements. While we continue to build strength in each of these cornerstones, today we will focus on silicon platforms and our SenseMe algorithm library. To fully appreciate our silicon platform and roadmap strategy, it’s important to understand the advantages of our Customer Specific Standard Product or CSSP business model. This model leverages the core IP advantage of our patent pending ultra-low power reprogrammable logic technology. With this model, we can deploy new silicon platforms by leveraging the flexibility of our reprogrammable technology. This advantage enables us to lower development costs and risks while accelerating our time to market. It also establishes a feedback loop with our customers that helps us refine our silicon platform roadmap. Time to market is critical in these consumer markets. And this model allows us to quickly introduce market specific platform based on our mobile FPGAs. To optimize for power and cost, we hardened [ph] certain aspects of the design over time into what essentially becomes a programmable application specific standard product or a customer specific ASSP. The programmable capabilities of platform allows our customers to tailor it to their specific needs. This entire model is enabled by the fact we have our programmable logic technology. The ArcticLink 3 S1 that we released in October 2013 is a perfect example of this model in action. While certain generic aspects of the S1 platform where implemented in hard logic, virtually everything else was done inside our in-system reprogrammable logic. This allowed us to immediately initiate design activities with targeted customers, and benefit from their feedback as we defined our S2 platform. Through this process, we were able to improve the design, move more functions into hard and logic blocks and increase the amount of programmable logic that customers can use for further hardware customization in our S2 platform. These early engagements also allowed us to move the first design wins in the preproduction approximately one-year after the release with the S1. We have continued to leverage this strategy with our ArcticLink 3 platform. I'll get into more detail on the S3 in a few minutes. Our SenseMe algorithm initiative which is only a year-old is playing out very well. In independent customer tests, applications driven by our proprietary algorithms have set new standard for accuracy and power efficiency. This and the ability to get a complete silicon and algorithm solution from one source has been widely embraced by our customers. Literally every current design that is scheduled to move into production is based on QuickLogic’s SenseMe library. Interestingly, a number of potential customers have expressed a desire to license our SenseMe algorithms ahead of adopting our silicon platforms. These include major participants in the wearable and smartphone markets. In most cases these customers are not at a point in their design cycle that would allow them to easily adopt our silicon platforms. These potential customers have indicated a strong interest in adopting our silicon in future designs. Establishing SenseMe license contract will help us secure commitments for our silicon in those designs. Most algorithms we’ve released so far are considered fundamental. These type of algorithms are commonly used in wearable devices and smartphones today and have enabled us to develop a substantial number of design engagements. A vast majority of our targeted customers want to include a fitness application in their solution and pedometer accuracy has become a very important factor in the selection process. While the pedometer function may seem simple, developing a robust algorithm that delivers accuracy independent of device location, stride, cadence, gender, age and height is a huge accomplishment. As mentioned last quarter, we have applied for a patent protection for this pedometer implementation. In addition to the near-term benefits of our SenseMe library, we’re leveraging these fundamental blocks to deploy more sophisticated algorithms such as our motion compensated heart rate monitor technology that we expect to release early in the second half of the year. This is the first of two line charts I'll show you today. This chart conveys quite a bit of information, so please bear with me as I walk you through it. The power consumption for embedded processor solutions is highly depending on something known as duty cycle. Duty cycle is the percentage of time the processor is turned on to execute instructions. The industry standard terminology for measuring the number of instructions in algorithm requires is MIPS or Millions of Instructions Per Second. The bottom line is the higher the MIPS, the higher the duty cycle requirement, and the more power you will consume. This chart shows MIPS along the horizontal axis. On the vertical axis it shows the corresponding power consumption for our recently announced ArcticLink 3 S2 LP platform and the typical arm M4F processor. Below the horizontal axis are the types of algorithms that are commonly being executed in smartphone and wearable devices today. When using our highly efficient SenseMe algorithms, we can satisfy most of the use cases inside a 0.4 MIPS window, which for our S2 LP platform means an active power consumption of 75 microwatts. A typical M4F solution would more likely have to run at/or above 1 MIPS to satisfy these use cases. While that implies substantially higher power consumption relative to the S2 LP, it is still within the power budget of most smartphone designs. To date the smartphone industry has followed a logical design progression with sensor processing shifting from an ARM core and an application processor to an embedded ARM core and a sensor hub. This was an easy and low-risk decision for designers, because as long as the process -- the MIPS processing requirements and corresponding duty cycle remain low; the power consumption is not terribly disruptive to battery life. However, that is not the case for small wearable devices. Smartphone battery capacity can be as much as 100 times greater than the battery capacity of small wearable devices like fitness bands and smartwatches. This is one of the reasons why our sensor processing system solutions are being so readily embraced by wearable device manufacturers. However, technology standstill for no one and leading smartphone manufacturers are telling us they want to significantly increase the MIPS capabilities of the sensor processing system. As you'll see in the next slide this means they are going to have to take a different design approach. Chart two zooms out to show what we believe will be the evolutionary path for sensor processing in smartphones. To put this in perspective, the previous chart fits into the small area to the left of the 1 MIPS label on the horizontal axis. Smartphone manufacturers seem to be comfortable working with solutions they can operate within the power consumption shown in the green band. This implies that the ARM M4F solutions that are commonly used in smartphone designs today have some headroom. However, due to the evolutionary trends we see in the industry there is not as much headroom as the chart suggests. Below the horizontal axis, you will see icons representing some of the sophisticated next-generation algorithms that smartphones and wearable design manufacturers would like to deploy. Since some of these algorithms require 20 or more MIPS each, the aggregate MIPS requirement is poised to move up significantly and in large steps. As that happens, the power consumption of the M4F solutions moves quickly through the yellow zone and into the red zone. The implication here is we believe there will be an emerging requirement to accommodate substantially higher MIPS at lower power levels than traditional embedded processor solutions can deliver. There are three things we believe will drive the demand for higher MIPS capabilities. First, there will be more data from more sensors to manage fuse and process more frequent data streams, require more MIPS and that means higher power consumption. Second, sophisticated algorithms are needed to drive next-generation applications like those shown across the bottom of the chart. More complex algorithms require more MIPS and with that higher power consumption. Third, design trends suggest we are finally moving towards always-on and always-aware applications. This will require higher duty cycles and as I noted earlier, higher duty cycles drive higher power consumption. As you can see from the line showing a typical embedded M4F processor solution, its power consumption moves into the yellow zone at only 24 MIPS and then into the red zone at 48 MIPS. This means that smartphone OEMs will have to take a different design approach if they want to keep pace with this evolutionary trend. We believe our next-generation sensor processing platform, the ArcticLink S3 is the right solution to support and enable this trend. The S3 remains on schedule for release during mid 2015. As you can see, the S3 is a revolutionary step up from our S1 and S2 platforms. Rather than being MIPS limited like our S1 and S2, it is targeted to deliver nearly 50% more MIPS capability than the typical embedded M4F processor solution. Now let's draw our attention to the middle of the chart, where you can see an inflection of the S3 power consumption at 55 MIPS. I am not going to reveal the unique architecture we have leveraged to keep the S3 power consumption so low at 55 MIPS. But I do want to highlight that typical M4F solution consumes seven times more power than our S3 and enters a smartphone red zone at only 48 MIPS. 55 MIPS is a critical design point for two reasons. First, we believe we can deliver most of the next-generation applications inside the 55 MIPS window and that means our solution is well within the smartphone green zone. As a matter of fact, we stay in the green zone all the way up to 94 MIPS which is more than four times the 23 MIPS, a typical M4F solution can deliver in the green zone. Second, is the fact that wearable device manufacturers would also like to take advantage of high value applications that sophisticated algorithms can deliver, with a targeted power consumption of only 1.65 milliwatts at 55 MIPS. The S3 can do that within what most wearable device manufacturers consider to be tolerable power budget. To put this in perspective, a typical M4F consumes about the same power, but only at 8 MIPS. And there is one more thing I’d like to share with you about the S3 platform. The S3 was intentionally designed to enable manufacturers that are currently embedded ARM solutions to easily port their intellectual property to the S3 platform. That means in addition to having what we believe is the right technical solution; we also present a low-risk migration path for our customers that leverages the economic benefits of integration. During our last conference call, we said that we had initiated ArcticLink S3 discussions with select customers under NDA. These discussions are going very well and we’ve evaluated request from customers that want to be part of our alpha program, which allows first access to this platform. We have had strong interest in this program and we have established full requirements for OEM participation. Members of our S3 alpha program must be top tier OEMs, have a specific and funded project, have executive sponsorship, and have agreed to establish a formal feedback with QuickLogic. We have recently established our first S3 alpha engagement with a top five smartphone company and we’re working to establish an engagement with the second smartphone company this quarter. That brings us to the end of our slide presentation. Now let me take a minute to review our new product activities in Q1 and our outlook for Q2. During Q1, we shipped development quantities of our S2 platform to a total of seven customers to support their design efforts on nine unique products. The three designs we forecasted for production shipments last quarter were delayed due to customer design changes. Including these three, we expect to ship units to support five production designs during Q2. We have received preproduction orders for three of these designs. In smart connectivity and display, we continue to support a variety of designs in North America, Japan, China, and South Korea. These include two new tablets from Samsung, the Tab 3 V and the Tab E7.0. I’d like to turn the call over to Ralph who will provide our Q2 guidance and then I’ll return for my closing remarks and Q&A.