Yes, just -- if I could add to that and, one, just as a cleanup to question that Aashish asked, our other products grew 22% sequentially. Remember that we put Enpirion in our other products, so it looks like the other products are up a lot. But also remember that category as a total is so very small, that just adding the Enpirion revenue, which was very small, caused that category to go up a lot and it's really the right place to put it because Enpirion is not a CPLD and it's not an FPGA. In terms of Intel, I think it's important to kind of walk through the cost structure and why we believe that choosing Intel was the right technology, specifically for us and for the high end. Just to talk -- and maybe it's worthwhile to take a step back and look at what's been offered from TSMC. So we're implementing our Arria 10, which is a midrange product in the 20-nanometer SoC product, which is a great midrange, has the right cost structure and future set for that. As we've also seen in the press, 16FF, which is TSMC's FinFET process, does not scale from 20 SoC. So what that means is, if you implement a design or the same design in 16FF, it results from the same die size as what you had in 20 SoC. As our competition also announced in their recent press release -- or press -- excuse me, quarterly announcement, they mentioned that a 16FF wafer is more expensive than a 20 SoC wafer simply because of the extra processing steps, which makes sense because the FinFET is more complicated to manufacture. All of which means if you take a design and move from 20 SoC to 16FF, the resulting die is more expensive to implement and your product, therefore, is going to cost more. We're working with Intel with 14-nanometer. Intel has a true 14-nanometer technology, which means that the product scales, you're getting much smaller die size. And therefore, your cost moving to Intel's 14-nanometer decreases, which is exactly what Intel has discussed publicly, where they've said that, as they forward to 14 and then to 10, Moore's Law will continue and Moore's Law, of course, is the doubling of transistors with a corresponding cost reduction. So we think from a cost standpoint, we've made the right move in moving to 14FF. Beyond that, outside of having a cost advantage over the competition, obviously at the high end, what we'll also have is -- because we're in a 14-nanometer transistor, we'll have a performance advantage, we'll have a power advantage. And then also because we're in a much smaller geometry [ph] process technology, we can make much more highly integrated devices, which means we're also have a density advantage. So this is why we say moving to the high end, our competition is somewhat trapped in that they're going to try to compete with us with a more expensive technology. We've got really a more cost-effective technology combined with better feature set. And we don't see anything coming on the horizon in the foundry industry, which really will catch up over the next 5 years, which is why I comfortably say that for the next 5 years, we will own the high-end. And as we've talked about before and our competition has as well, the high-end is half of the FPGA industry in revenue. So I just wanted to follow up with that because similar question was around why Intel, and I think it's important to understand that scaling that process advantage, that node advantage is really critical to high end, and that's what we get with Intel.